Job Description

About the Company

As a Design Verification Engineer/Hardware Verification Engineer, you will work closely with our RTL development engineers, system architects, and software engineers to verify functional correctness and robustness of the RTL powering our next generation, FPGA-based secure communications systems.

About the Role

As a Design / Hardware Verification Engineer, you will be responsible for hands‑on RTL verification using SystemVerilog and UVM for FPGA‑based secure communications systems.

You will design, implement, and maintain UVM verification environments , including testbenches, sequences, drivers, monitors, and scoreboards. This role involves executing constrained‑random and directed tests to verify RTL functionality at both block and system levels.

A core part of the job is debugging RTL and verification failures in simulation , analyzing waveforms, triaging issues with RTL designers, and driving bugs to closure. You will also collect and analyze functional and code coverage and maintain simulation regressions.

This is a code‑centric verification role that requires strong individual contribution in SystemVerilog/UVM , with close day‑to‑day collaboration with RTL engineers.

Responsibilities

• Own the verification of custom RTL blocks, subsystems, and full FPGA-level functionality
• Work with RTL design engineers and system architects to define verification plans based on system specifications, design goals, and use cases
• Develop and maintain verification environment in SystemVerilog/UVM including constrained-random, directed, and system-level testbenches
• Develop and maintain stimulus generators, drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces
• Work closely with RTL design engineers to triage and resolve bugs, owning and driving technical issues to resolution
• Collect and report code and functional coverage
• Maintain regular simulation regressions

Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
• 5+ years experience in hardware verification using SystemVerilog/UVM
• Proven success verifying complex RTL designs in industry-standard flows, including creation and maintenance of verification environment, test benches, and test cases
• Proficient in SystemVerilog, UVM, and common simulation and debug tools including Siemens Questa
• Proficient in Writing UVM Test Code
• Experience with Object Oriented Programming
• Experience with industry standard EDA tools (Cadence, Synopsys, and/or Mentor)
• Foundational knowledge of digital logic and timing considerations
• Strong written and verbal communication skills, ability to work with a geographically distributed team
• Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
• Desire to be a member of a team, collaborating on large system designs
• Work independently, take initiative, and take ownership of tasks and results
• US citizenship required
• Active United States Secret Security Clearance
• Ability to travel up to 10%

This role is focused on writing verification code and is not a systems engineering, validation, or integration‑and‑test position.

Pay range and compensation package

This is a 100% on-site role working from our office in one of these locations: Carlsbad, CA, or Marlborough, MA.

Equal Opportunity Statement

We are committed to diversity and inclusivity.

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